Communication protocol processing unit formed by multiprocessor

ABSTRACT

A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a communication protocolprocessing unit, which executes a communication protocol process such asATM, SDH, or the like by a processor.

[0003] 2. Description of the Related Arts

[0004] In order to process a high-speed communication protocol in theprior art, each process in the communication protocol such as ATM, SDH,or the like is performed by a hardware configuration (Hard Wired) in ageneric technology.

[0005] For this reason, each time a standard recommended specificationsuch as ITU-T, or the like or a small-scaled specification is changedand added, it is necessary to redesign a hardware structure, which hasbecome a problem in view of technology and cost.

[0006] Furthermore, in order to avoid such the problem, when it isconsidered that a processor performs the high-speed communicationprotocol process, an enormous band width is required for a highperformance in the processor.

[0007] In particular, in the case where a plurality of connectionprocesses such as an ATM cell process are made to handle an enormousdata amount at a high speed, the realizability was made difficult fromprocessing capability, a required band width, or the like which isdemanded for the processor in performing a processor processing.

[0008]FIG. 1 is a diagram for explaining such conventional problems bymentioning the ATM cell process as an example. In the case where for anATM cell throughput of 600 Mbps through a memory function 4 such as amemory, or the like, all functions (cell discrimination, UPC, NDC, OAM,accounting, header change, etc.) on an ATM layer of the ITU-Trecommendation is executed by a processor 1 based on instructions storedin an instruction memory 3, an enormous band width such as 10 Gbps ormore is required in a data transfer relative to a parameter 2 stored ina data RAM, or the like per cell process in the processor 1 in view of ahandling data amount.

[0009] Furthermore, it was demanded that a processor would have toperform a processing within 1 cell time (680 ns), etc, but it becamedifficult to realize such the processor capable of corresponding to suchthe demand.

SUMMARY OF THE INVENTION

[0010] It is therefore an object of the present invention to provide acommunication protocol processing unit capable of mitigating a necessarycondition such as performance, a band width, or the like of theprocessor as a structural element, and performing a communicationprotocol process by the processor at lower costs as a whole.

[0011] According to the present invention attaining the above-describedproblems, a communication protocol processing unit formed by amultiprocessor has a first processor for performing a process demandinga real time property in a communication data stream; and a secondprocessor for performing a process not demanding a real time property,wherein the first processor transfers to the second processor useparameters paired with communication data to be processed, and thesecond processor is configured so as to refer to the transferredcommunication data and parameters for processing.

[0012] Furthermore, in an preferred aspect of the communication protocolprocessing unit by the multiprocessor according to the present inventionattaining the above-described problem, the communication protocolprocessing unit comprises a process queue for storing the pair of thecommunication data and parameters between the first and secondprocessors.

[0013] Furthermore, in a preferred aspect of the communication protocolprocessing unit by the multiprocessor according to the present inventionattaining the above-described object, the first processor is configuredso as to generate a processing demand signal which demands a process tothe second processor, before the first processor generates the processdemand signal, the communication data and parameters have beenpreviously unconditionally transferred to the process queue, and theprocess queue can display independently validity/invalidity of the dataalready transferred to the process queue according to presence orabsence of the process demand signal from the first processor.

[0014] Furthermore, in a preferred aspect of the communication protocolprocessing unit by the multiprocessor according to the present inventionattaining the above-described problem, a plurality of the firstprocessors are provided, and are in series arranged to pipeline, andeach of the plurality of first processors is demandable for processingto the second processor.

[0015] Furthermore, in a preferred aspect of the communication protocolprocessing unit by the multiprocessor according to the present inventionattaining the above-described problem, the communication protocolprocessing unit further comprises a queue for storing processing resultsof the second processor between the first and second processors; and aselecting circuit as means for overwriting the communication data in thestream to the processing results of the second processor, wherein thefirst processor read-accesses the queue, and when the data areaccumulated in the queue, the selection route of the selecting circuitis switched into a queue side.

[0016] The features of the present invention will become more apparentfrom the embodiments thereof set forth in light of the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a diagram showing a conventional example in the casewhere an ATM cell process is performed by a processor;

[0018]FIG. 2 is a block diagram showing the configuration of a firstembodiment;

[0019]FIG. 3 is an operational sequence flow corresponding to theconfiguration of FIG. 2;

[0020]FIG. 4 is an operational time chart corresponding to theconfiguration of FIG. 2;

[0021]FIG. 5 is a diagram for explaining a contradiction of parameters;

[0022]FIG. 6 is a diagram for explaining the case where theconfiguration of FIG. 2 according to the embodiment of the presentinvention is applied to a performance monitoring processing (ITU-Trecommendation I.610) in the ATM cell processing;

[0023]FIG. 7 is an operational time chart of FIG. 6;

[0024]FIGS. 8A to 8C are diagrams for explaining a sense of theperformance monitoring processing in the ATM cell processing;

[0025]FIG. 9 is a diagram showing the conventional example of theperformance monitoring processing in the ATM cell processing;

[0026]FIG. 10 is a diagram showing an example according to a secondembodiment of the present invention;

[0027]FIG. 11 is a diagram showing an operational sequence according tothe embodiment of FIG. 10;

[0028]FIG. 12 is a diagram showing an operational flowchart of FIG. 10;

[0029]FIGS. 13A & 13B are diagrams showing the operational flowchart ofFIG. 10;

[0030]FIG. 14 is further a diagram showing a configuration according toa third embodiment;

[0031]FIG. 15 is a diagram for explaining a process of a processingdemand of FIG. 14;

[0032]FIG. 16 is an embodiment of a function of forwarding theprocessing demands of real time processing processors 100-1 to 100-3 inFIG. 14;

[0033]FIG. 17 is a diagram showing an operational sequence according toa fourth embodiment of the present invention to be realized in theconfiguration of FIG. 2;

[0034]FIG. 18 is a diagram showing an operational time chart of FIG. 17;and

[0035]FIG. 19 is an example of a preferable configuration which realizesthe operational time chart according to the embodiment of FIG. 17.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Hereinafter, embodiments of the present invention will bedescribed with reference to the drawings. Incidentally, the embodimentsillustrated are for understanding of the present invention, and theapplication of the present invention is not restricted thereto.

[0037]FIG. 2 is a structural block diagram according to a firstembodiment of the present invention. FIGS. 3 and 4 are an operationalsequence flow and an operational time chart in response to theconfiguration of FIG. 2, respectively.

[0038] In order to mitigate a necessary condition for performing aprocessor process, in the present invention, the process is partitionedinto a processor needing a real time property and a processor notneeding the real time property.

[0039] In FIG. 2, this embodiment includes a processor 10-1 forperforming in a forward process demanding the real time property and aprocessor 10-2 for performing a backward process (hereinaftergenerically referred to as a real time processing processor 10); and aprocessor 11 for performing a process not demanding the real timeproperty (hereinafter referred to as a non-real time processingprocessor 11).

[0040] In FIG. 2, instruction memories 3-1, 3-2, 3-3 are memories forstoring instructions for the processors 10, 11, respectively.

[0041] In the case of dividing into the real time processing processor10 and non-real time processing processor 11, when parameters are storedin a data RAM 2 or the like and accessed by both the processors, acontradiction of parameter values occurs due to a difference inrespective processor processing times, and such a problem occurs.

[0042] Incidentally, here, the parameters are memory data required for aprocess excluding communication data, for example, state transitionalinformation, statistical information, various setting information, andthe like.

[0043]FIG. 5 is a diagram for explaining a contradiction of suchparameters.

[0044] In the case where a reception event of the communication datagenerates according to a time as in communication data 1, 2, 3 as shownin FIG. 5, the non-real time processing processor 11 needs to beprocessed with a value of parameters (A) as X when processing thecommunication data 1.

[0045] However, a renewal of the parameters (A) to Y with respect to thecommunication data 3 received later has been already made by the realtime processing processor 10. Accordingly, when the non-real timeprocessing processor 11 refers to renewal data X of the parameters (A),X has been already renewed to Y, and as this is referred to, acontradiction occurs.

[0046] Here, in FIG. 2, in order to avoid the occurrence of suchcontradiction, it is considered that the processings handle theparameters to be accessed by both the real time processing processor 10and non-real time processing processor 11, and are owed only to a realtime processing processor 10. However,this causes to increase theprocess load of the real time processing processor 10.

[0047] Accordingly, according to the present invention, the real timeprocessing processor 10 generates, outputs, and processes a processingdemand to the non-real time processing processor 11 as communicationdata, which are paired with parameters for use in both the processors10, 11, and the pair is transferred to the non-real time processingprocessor 11.

[0048] The non-real time processing processor 11 processes by use of thetransferred communication data and parameters for reference, and in suchparameters, as not accessing memories such as a data RAM, or the likestoring the parameters 2, it is possible to avoid a contradiction of theparameters to be accessed by both the processors 10, 11.

[0049] As it is possible to disperse the process to the processor 11, itis possible to decrease a band width or performance demanded for theprocessor to process the communication data.

[0050] Such situation will be explained by use of FIGS. 3 and 4. FIG. 3shows an operational sequence between the real time processing processor10-1 for performing forward communication data and the non-real timeprocessing processor 11.

[0051] Each time each of the communication data 1, 2, 3, . . . isgenerated, the real time processing processor 10-1 accesses theparameters 2 in response to the instruction from an instruction memory3-1, and performs an arithmetic process (processing steps P1, 2, 3, 4,5).

[0052] When queue write data are generated (at the time of theprocessing step P2 of the communication data 2 in FIG. 3), theparameters, communication data, or the like are written into a processqueue 14-1 (process step P6). In FIG. 4, after the real time processingprocessor 10-1 processes the communication data 2, a status of theprocess queue 14-1 is changed to “1.”

[0053] On the other hand, the non-real time processing processor 11makes periodically a polling to the process queue 14-1 (process stepP7). When demand data exist in the process queue 14-1 in a process ofthe polling, the non-real time processing processor 11 reads contents ofthe queue (process step P8), and performs an arithmetic process (processstep P9).

[0054] When this arithmetic process is ended, the polling restarts(processing step P10). At this time, a status of the processing queue14-1 is changed to “0.”

[0055]FIG. 6 is a diagram for explaining the case where theconfiguration of FIG. 2 applies to a performance monitor process (ITU-Trecommendation I.610) in the ATM cell process according to the firstembodiment of the present invention. FIG. 7 is an operational time chartof FIG. 6. FIG. 6 shows a configuration of only a reception side of theATM cell for brevity of the description, and further the instructionmemory is not shown.

[0056] The sense of the performance monitor process in the ATM cellprocess is as shown in FIGS. 8A to 8C. FIGS. 8A and 8B show a cell flowfor one connection. FIG. 8A shows the cell flow from an ATM celltransmission side. N pieces of user cell having minimum 128 pieces arecontinued, and after the N pieces of user cell, the number of user cellsand calculated parity (BIP: Bit Interleaved Parity) are annexed to apayload of FPM (Forward Performance Monitoring) for transmission.

[0057]FIG. 8B is an ATM cell flow to be received at an ATM cellreception side. The number of user cells received is counted, and aparity is acquired. Furthermore, the payload of the succeeding FPM(Forward Performance Monitoring) cells is annexed to the number of usercells and parity at the transmission side for comparison. Thus, thenumber of discarded cells, the number of faultily delivered cells, andthe number of error bits when received are judged.

[0058]FIG. 8C shows the ATM cell flow when aiming at a plurality ofconnections. A connection ID is assigned to the cells configured in eachframe. The number of user cells received is counted in each connection,and a BIP-16 arithmetic process is performed for a payload region of theuser cells of the corresponding connection ID (hereinafter referred toas an intermediate measuring process).

[0059] Next, based on results of the intermediate measuring process ofthe user cells flowing between the reception FPM cells, it is possibleto realize a performance monitoring function by collecting thestatistics of the number of discaded cells, the number of faultilydelivered cells, and the number of error bits (hereinafter referred toas a statistical process).

[0060] Incidentally, a transmission interval of the FPM cells areprovided in the ITU-T recommendation I.610 (FIG. 8C) and is defined as atransmission of 1 cell in each minimum 128 cells.

[0061] Returning to FIG. 6, the above intermediate measuring process isassigned to the real time processing processor 10-1, and the statisticalprocess is assigned to the non-real time processing processor 11. Inthis case, the parameters 2 required for the real time processingprocessor 10-1 areas {circle over (1)} the number of reception user cellcount; and {circle over (2)} BIP-16 calculation values. The parameters 2required for the non-real time processing processor 11 are {circle over(2)} the number of reception user cell count; {circle over (2)} BIP-16calculation values; and additionally {circle over (3)} the number ofdiscarded cells; {circle over (4)} the number of faultily deliveredcells; and {circle over (5)} the number of error bits.

[0062] The parameters mentioned here are ones for both the reference andrenewal, and in addition, the parameters for only reference exist, andas they do not have direct connection with the present invention, thedescription is omitted.

[0063] As described above, {circle over (1)} the number of receptionuser cell count; and {circle over (2)} the BIP-16 calculation values areparameters required for both the real time processing processor 10-1 andnon-real time processing processor 11.

[0064] When receiving the user cells (FIG. 7a), the real time processingprocessor 10-1 renews the parameters of {circle over (1)} the number ofreception user cell count; and {circle over (2)} the BIP-16 calculationvalues as the intermediate measuring process (FIG. 7b) (FIGS. 7c and 7d).

[0065] Furthermore, when receiving the FPM cells, the parameters of{circle over (1)} the number of reception user cell count; and {circleover (2)} the BIP-16 calculation values are transferred to the non-realtime processing processor 11 (or the process queue 14-1) together withthe reception FPM cell (FIG. 7e), and these parameters are reset (FIGS.7c and 7 d).

[0066] The non-real time processing processor 11 statistically processesthe transferred parameters of {circle over (1)} the number of receptionuser cell count; and {circle over (2)} the BIP-16 calculation values,and uses the FPM reception cells to calculate {circle over (3)} thenumber of discarded cells, {circle over (4)} the number of faultilydelivered cells, and {circle over (5)} the number of error bits (FIG.7f).

[0067] Continuously, the parameters of by {circle over (3)} the numberof discarded cells, {circle over (4)} the number of faultily deliveredcells, and {circle over (5)} the bits which are calculated are renewed(FIGS. 7g, 7 h, and 7 i).

[0068] Hereinabove, it is possible to disperse the performancemonitoring process (ITU-T recommendation I.610) in the ATM cell processto the real time processing processor 10-1 and non-real time processingprocessor 11.

[0069] Thus, as effects, in the case where

[0070] in a throughput of the ATM cell flow, 1 cell time=T;

[0071] the number of program processing execution step of theintermediate measuring process: A;

[0072] the number of program processing execution step of thestatistical process: B;

[0073] the parameters of {circle over (1)} the number of reception usercell count, and {circle over (2)} the BIP-16 calculation values: 16 bitseach; and

[0074] the parameters of {circle over (3)} the number of discardedcells, {circle over (4)} the number of faultily delivered cells, and{circle over (5)} the error bits: 32 bits each,

[0075] in the case where the configuration of the conventional exampleshown in FIG. 1 is adapted for the performance monitoring process in theATM cell process, as shown in FIG. 9, a band width (bit/s) required forthe processor 10-1 is set to 128/T (=(16×2+32×3)/T), and a performance(step/s) required for the processor 10-1 is set to (A+B)/T.

[0076] On the other hand, as, with the configuration according to thepresent invention, a reception interval of the FPM cells is once per 128cells, the band width required for the real time processing processor10-1 is set to 32/T (=(16×2)/T), and the band width required for thenon-real time processing processor 11 is set to 0.75/T (=(32×3)/128T),and the performance required for the real time processing processor 10-1is set to A/T, and the performance required for the non-real timeprocessing processor 11 is set to B/128T.

[0077] As the results, the performance required for the processor andthe necessary band width can be decreased. Incidentally, the handlingparameters are actually more than those mentioned in the above example(in particular, the statistical parameters), and it is apprehensiblethat effects of the present invention become further larger.

[0078] Furthermore, as shown in FIG. 8C, in the case where theperformance monitoring is performed to a plurality of connections, thenon-real time processing processor 11 retains the communication data andparameters which are transferred from the real time processing processor10-1. This embodiment includes the processing queue 14-1 to the non-realtime processing processor 11.

[0079] Thus, even if the FPM cells are continuously received and theprocess of the non-real time processing processor 11 is continuouslydemanded, they have only to be stored in the queue 14-1. The need forincreasing the processing capability of the processor does not occur.

[0080] In the performance monitoring process, in order to transmit theFPM cells in each transmission of minimum 128 user cells in eachconnection, the FPM cells of the plurality of connections arecontinuously received, and even if the process of the non-real timeprocessing processor 11 is continuously demanded, in the case where theFPM cells are next received to demand the process of the non-real timeprocessing processor 11, the demand is after 128 cells at a minimum(refer to FIG. 8C).

[0081] Accordingly, with the provision of the process queue 14-1 (thenumber of stages is set to be the number of FPM cells or over which arecontinuously received), the statistical process has only to end within a128-cell time, and it is not necessary that the processing capability ofthe non-real time processing processor 11 is increased.

[0082] As mentioned above, according to the present invention, the realtime processing and non-real time processing processor 10, 11 areprovided. The parameters to be used by both the processors (the memorydata to be used for processes excluding the communication data) aretransferred to the non-real time processing processor 11 in pairs withthe communication data to be processed.

[0083] As the non-real time processing processor 11 performs thestatistical process for use in the transferred communication data andparameters for reference, no contradictions in the parameters by boththe processor processing times occur. Accordingly, the process can bedispersed to the real time processing processor 10 and the non-real timeprocessing processor 11, and it is possible to mitigate necessaryconditions such as performance, band widths, or the like of theprocessor configuring a system.

[0084] According to the present invention, it is possible to constructthe communication protocol processing unit in which the communicationprotocol process is performed by the processor at lower costs as awhole.

[0085] Furthermore, according to the present invention, when the realtime processing processor 10 demands the process to the non-real timeprocessing processor 11, the necessary data are only written into thequeue 14-1 as a process demand. Therefore, taking into considerationoccurrence frequencies of the processing demand, the non-real timeprocessing processor 11 can reduce the processing capability down tosuch a degree that an overflow of the queue 14-1 does not generate.Furthermore, it is possible to process the communication data which werecontinuously received without a disorder of a communication data stream.

[0086]FIG. 10 is a diagram showing a second embodiment of the presentinvention, indicating only a part in which the communication data andparameters are transferred to the processing queue 14-1. According tothe second embodiment of FIG. 10, a DMA control circuit 20 is furtherprovided so as to control a data transfer of a local memory 10-3 such asa cash, a register, or the like of the memory 4-1 and the real timeprocessing processor 10-1.

[0087]FIG. 11 shows an operational sequence according to the secondembodiment of FIG. 10. Furthermore, FIG. 12 shows an operationalflowchart, and FIG. 13 shows an operational time chart.

[0088] According to the second embodiment, when the real time processingprocessor 10-1 receives the communication data, the processor 10-1activates the DMA control circuit 20, and further accesses theparameters 2, and before the processor 10-1 demands the process of thecommunication data and parameters to the non-real time processingprocessor 11, the processor 10-1 first unconditionally transfers thecommunication data and parameters to the process queue 14-1 (refer to Iand II of FIG. 11).

[0089] In the example of FIG. 11, in this case, the communication data 1are not demanded for the process to the non-real time processingprocessor 11, and the communication data 2 are demanded for the process.Accordingly, when the process is demanded by the arithmetic process withrespect to the communication data 2, the demand for the process isnotified to the process queue 14-1 (refer to III of FIG. 11).

[0090] The management of the process queue 14-1 is executed by a writepointer and a read pointer. When the process is demanded, the writepointer is increased, and the non-real time processing processor 11polls these pointers, and it is recognized that valid data are stored inthe processing queue 14-1 according to disagreement of the write pointerwith the read pointer.

[0091] In the case where it is recognized that the valid data are storedin the processing queue 14-1, the non-real time processing processor 11increases the read pointer, and starts the processing (refer to IV ofFIG. 11).

[0092]FIG. 12 is a detailed operational flowchart in response to theoperational sequence of FIG. 11. The real time processing processor 10-1monitors the memory 4-1, and judges presence or absence of reception ofthe communication data (processing step P20). When the processor 10-1receives the communication data (processing step P20; Yes), theprocessor 10-1 activates the DMA control circuit 20 (processing stepP21).

[0093] When the processor 10-1 activates the DMA control circuit 20, theprocessor 10-1 controls to transfer the communication data andparameters to the processing queue 14-1 (processing step P22).

[0094] On the other hand, when the real time processing processor 10-1receives the communication data (processing step P20; Yes), theprocessor 10-1 is transferred the parameters 2 (processing step P23),and performs the arithmetic processing (processing step S24).

[0095] As the results of this processing, if the processing is demanded(processing step P25; Yes), the write pointer of the processing queue14-1 is increased (processing step P26). On the other hand, if theprocessing is not demanded at processing step P25, the transfer of thecommunication data to the processing queue 14-1 is invalidated, thewrite pointer is not increased (processing step P27).

[0096]FIGS. 13A & 13B are diagrams for explaining effects of theembodiment of FIG. 10. In FIG. 13A, after the communication data areperformed the arithmetic process, the parameters and communication dataare written into the processing queue 14-1.

[0097] On the contrary, in the processing of FIG. 13B in response to theembodiment of FIG. 10, at the same time as the communication data arereceived, the parameters and communication data are transferred to theprocessing queue 14-1 by the DMA control circuit 20. Accordingly, incomparison with FIG. 13A, it is possible to decrease a transfer time (T)of the communication data and parameters, and to enhance the throughputof the communication data in proportion to the decrease time.

[0098] In this manner, according to the embodiment of FIG. 10, beforethe real time processing processor 10-1 demands the processing to thenon-real time processing processor 11, the data required for thenon-real time processing processor 11 have previously been transferredto the queue 14-1. For this reason, even if the handling communicationdata amount is enormous, it is possible to shorten a time from theoccurrence of processing demands to the completion of the data transfer.It is possible to enhance the throughput of the communication data inproportion to this shortened time, or to reduce performance of theprocessor.

[0099] Here, according to the embodiment of FIG. 10, when thecommunication data are received not via the processor with the receptionof the communication data as an event, the communication data aredirectly transferred to the processing queue 14-1 in the DMA transfer.For this reason, a separate data bus from a bus provided between theprocessor 10-1 and the communication data storing memory 4-1 is providedto make the data transfer, so that a load of the processor 10-1 can bedecreased.

[0100] In the case where, for example, the ATM cell is assumed as thecommunication data, they forms an enormous data transfer of 53 bytes,and it is seemed that a load of the processor 10-1 is increased, butaccording to the present invention, since the processing of theprocessor 10-1 is independent of the transfer of the ATM cell, the loadof the processor 10-1 can be decreased.

[0101]FIG. 14 is a diagram showing a configuration according to a thirdembodiment. In the third embodiment, in the case where there are verymany processings demanding a real time property, or in the case where asingle real time processing processor 10-1 cannot fully process, in thisconfiguration, a plurality of real time processing processors 100-1 to100-3 are in series arranged to pipeline-process.

[0102] In this case, it is assumed that there is a problem that a writecontention into the processing queue is generated by the plurality ofreal time processing processors 100-1 to 100-3, or that write data aremade redundant (in particular, when demanding the processing for thesame communication data).

[0103] To cope with the above, according to the present invention, theprocessing demands are forwarded to the latter step processor(processing demands 110-1 to 110-3, processing demands 110-4 to 110-5),and are finally collected by a merge circuit 21 to form one body,thereby generating the processing demand.

[0104] Accordingly, the write contention into the processing queue bythe plurality of real time processing processors 100-1 to 100-3 is notgenerated. Concurrently, a redundancy of the write data is notgenerated.

[0105] Furthermore, before the processing demands are forwarded to thelatter step processor and collected finally to set as one body, therebygenerating the processing demand, when the communication data(occasionally together with the parameters also) are transferred to theprocessing queue 14-1, in the same manner as in the embodiment of FIG.10, it is possible to decrease the transfer time of the communicationdata, and to enhance the throughput of the communication data inproportion to the decreased time.

[0106] Here, in FIG. 14, since the plurality of real time processingprocessors 100-1 to 100-3 forward the processing demands to transfer tothe processing queue 14-1, it is not necessary that forwarding memoryfunctions 110-1 to 110-6 are provided with the same capacity withrespect to all the real time processing processors 100-1 to 100-3.

[0107] That is, each processor accumulates the processing demands,whereby it is possible to decrease the capacity of the forwarding memoryfunctions in the pre-step processor and a forwarding signal number.

[0108]FIG. 15 is a diagram for explaining such a process of theprocessing demands of FIG. 14. In FIG. 15, for the receivedcommunication data a, the real time processing processor 100-1 generatesa processing demand 1 (refer to FIG. 15b). Accordingly, the processingdemands forwarded from the real time processing demand processor 100-1to the real time processing demand processor 100-2 are shown in FIG.15c.

[0109] On the contrary, the real time processing demand processor 100-2generates a processing demand 2 (refer to FIG. 15d). Accordingly, theprocessing demands forwarded from the real time processing demandprocessor 100-2 to the real time processing demand processor 100-3 areshown in FIG. 15e, collecting the processing demands forwarded from thereal time processing demand processor 100-1.

[0110] Furthermore, the real time processing demand processor 100-3generates a processing demand 3 (refer to FIG. 15f). Accordingly, theprocessing demands sent from the real time processing demand processor100-3 to the merge circuit 21 are shown in FIG. 15g, collecting theprocessing demands forwarded from the real time processing demandprocessor 100-2.

[0111] In this manner, each processor accumulates the processingdemands, whereby it is possible to decrease the capacity of theforwarding memory functions in the pre-step processor and the forwardingsignal number.

[0112]FIG. 16 is an embodiment of a function of forwarding theprocessing demands of the real time processing processors 100-1 to 100-3in FIG. 14, and a configuration diagram representing only a generationpart of the write data into the processing queue 14-1 and a generationpart of the processing demands.

[0113] Each of the real time processing processors 100-1 to 100-3forwards data required for the processing of a processing demand flag F,parameters DP, or the like in a next reception event of thecommunication data.

[0114] At the final step, the processing demands are generated by takinga disjunction of each processing demand flag F. Furthermore, the writedata (independently of the communication data) into the queue 14-1 areobtained by merging each data. Accordingly, the transfer to the queue14-1 can be made by managing a hardware, and as it is not necessary tomake the processing demands to the non-real time processing processor11, or generate the necessary data, the load of the real time processingprocessors 100-1 to 100-3 can be decreased.

[0115] According to the embodiment of FIG. 14, the processing demands tothe non-real time processing processors 11 by the plurality of real timeprocessing processors 100-1 to 100-3 are collectively compiled. Thus, itis possible to avoid the contention of the data transfers, or processingdemands to the processing queue 14-1 by the plurality of real timeprocessing processors 100-1 to 100-3, and further to remove a redundancyof data stored in the queue 14-1.

[0116] Furthermore, according to the embodiment of FIG. 14, before theprocessing demands to the non-real time processing processors 11 by theplurality of real time processing processors 100-1 to 100-3 arecollectively compiled and output, the data required for the non-realtime processing processors 11 are first transferred to the queue 14-1.Thus, even if the communication data amount to be handled is enormous,it is possible to reduce a time from the generation of the processingdemands to the completion of the data transfer, and to enhance thethroughput of the communication data in proportion to the reduced time,or to decrease performance of the processor.

[0117] Furthermore, according to the embodiment of FIG. 14, in order tocollectively compile the processing demands to the non-real timeprocessing processors 11 by the plurality of real time processingprocessors 100-1 to 100-3, this is a configuration in which the data tobe forwarded are accumulated by each processor, and forwarding costs fora capacity of memory functions, a forwarding capacity can be decreased.

[0118] Furthermore, in FIG. 14, it is possible to forward the processingdemands independently by the hardware with the reception of thecommunication data as the event, by shift operation by a shift register.In such the case, as it is not necessary that the processor itself makesoperation of forwarding the processing demands, the load of theprocessor can be decreased.

[0119]FIG. 17 is a diagram showing an operational sequence according toa fourth embodiment of the present invention, which is realized in theconfiguration of FIG. 2. FIG. 18 is an operational time chart of FIG.17. Namely, the operational sequence and operational time chart in thecase where the processing results of the non-real time processingprocessor 11 are utilized by the real time processing processor 10.

[0120] For this reason, in FIG. 2, selection circuits 17-1, 17-2 areprovided for selecting the memory functions 4-1, 4-2 of a memory, etc.for storing the communication data, and the queues 15-1, 15-2.

[0121] In FIGS. 17 and 18, in the same manner as in the above-describedembodiments, the forward data communication will be explained. The queue15-1 for storing the processing results of the non-real time processingprocessor 11, and the non-real time processing processor 11 write theprocessing results in the queue (FIG. 17, I). Accordingly, in FIG. 18, astatus of the queue 15-1 changes from “0” to “1” (FIG. 18,b).

[0122] On the other hand, in FIG. 17, in order to obtain the processingresults of the non-real time processing processor 11 in a process of insequence processing the communication data 1 to 3, the real timeprocessing processor 10-1 accesses to read the queue 15-1 by the programprocessing.

[0123] In the case where the communication data on a stream areoverwritten to the processing results of the non-real time processingprocessor 11, the queue 15-1 is read out, and when the data areaccumulated in the queue 15-1, a selection destination of the selectioncircuit 17-1 is switched to a side of the queue 15-1. Thus, it ispossible to reflect the processing results of the non-real timeprocessing processor 11 on the stream of the communication data (FIG.17, II; FIG. 18,d).

[0124] Here, as a method for managing the queue 15-1, in the same manneras in the operational sequence of FIG. 11, it is possible to realize themanaging method by a write pointer and a read pointer.

[0125] As an example in which the processing results of the non-realtime processing processor 11 are reflected on the stream of thecommunication data, there is an OAM cell insertion processing in an ATMcell communication system. In the case where an empty cell exists on astream of the ATM cell, in this process, the OAM cell is inserted into acorresponding cell slot.

[0126] The OAM cell generated in the non-real time processing processor11 has been written in the queue 15-1, and when the real time processingprocessor 10-1 detects the empty cell, it reads the queue 15-1, and whenthere are data, the selection destination of the selection circuit 17-1is switched to a side of the queue 15-1. Thus, the communication data inthe corresponding cell slot are overwritten to information read from thequeue 15-1.

[0127]FIG. 19 is a preferable configuration of an example which realizesthe operational sequence according to the embodiment of FIG. 17. In thequeue 15-1 for storing the processing results of the non-real timeprocessing processor 11, a register 22 indicating whether or not dataare accumulated, and a control circuit (a readout control circuit) 23for reading out the queue 15-1 are provided.

[0128] The non-real time processing processor 11 reads the register 22to recognize that the data are accumulated in the queue 15-1. In thisconfiguration, the readout control circuit 23 is activated when the dataare accumulated, whereby the readout control circuit 23 independentlyreads out the data of the queue 15-1 by the hardware not via theprocessor 10-1.

[0129] According to the embodiments of FIGS. 17 to 19, in the case wherethe data are accumulated in the queue 15-1 for storing the processingresults of the non-real time processing processor 11, the selectiondestination of the circuit 17-1 for selecting the output communicationdata is witched to a side of the queue 15-1. Accordingly, the processingresults of the non-real time processing processor 11 can be reflected onthe communication data flowing at a high speed.

[0130] Furthermore, according to the embodiments of FIGS. 17 to 19, thereal time processing processor 10-1 recognizes by register valueswhether or not the data are accumulated in the queue 15-1 for storingthe processing results of the non-real time processing processor 11, andthe readout of the queue 15-1 is executed not by the processor, but bythe control circuit 23 which reads out the queue 15-1. Therefore, theload of the processor 10-1 can be decreased. In this manner, the presentinvention is applicable to the ATM cell process which was realized bythe Hard Wired in the prior art, thereby mitigating a necessarycondition to the processor in the case where it is processed by theprocessor to realize the processing of the processor.

[0131] As explained above according to the embodiments with reference tothe drawings, according to the present invention, it is possible torealize that each process of the communication protocol such as ATM,SDH, or the like has been performed conventionally in the hardware (HardWired), and is performed by the processor, and each time a standardrecommendation specification of ITU-T, etc. or a small-scaledspecification is changed and added, it is unnecessary to again make ahardware design (remake), and this can be coped with by a change of aprogram. Also, it is possible to mitigate a necessary condition to theprocessor to be mounted (performance, a band width, or the like), and todecrease also unit costs of the apparatus.

What is claimed is:
 1. A communication protocol processing unit formedby a multiprocessor, comprising: a first processor for performing aprocess demanding a real time property on a stream of communicationdata; and a second processor for performing a process not demanding thereal time property, wherein the first processor transfers usingparameters paired with the communication data to be processed to thesecond processor, and the second processor is structured so as to referto the transferred communication data and parameters to process.
 2. Thecommunication protocol processing unit by a multiprocessor according toclaim 1, wherein the parameters are state transitional information,statistical information, or various setting information which is neededfor a process excluding the communication data.
 3. The communicationprotocol processing unit by a multiprocessor according to claim 1,further comprising: a processing queue provided between the first andsecond processors, for storing a pair of the communication data andparameters.
 4. The communication protocol processing unit by amultiprocessor according to claim 3, wherein the first processor isstructured so as to generate a processing demand signal for demandingthe processing to the second processor, before the first processorgenerates the processing demand signal, the communication data andparameters are first unconditionally transferred to the processingqueue, and the processing queue can independently displayvalidity/invalidity of the transferred data to the processing queueaccording to presence or absence of the processing demand signal fromthe first processor.
 5. A communication protocol processing unit by amultiprocessor comprising: a plurality of first processors arranged inseries to pipeline-process for performing a process demanding a realtime property on a stream of communication data; and a second processorfor performing a process not demanding the real time property, whereineach of the first processors transfers using parameters paired with thecommunication data to be processed to the second processor, and thesecond processor is structured so as to refer to the transferredcommunication data and parameters to process.
 6. The communicationprotocol processing unit by a multiprocessor according to claim 5,wherein each of the plurality of first processors is structured so as togenerate the processing demand to the second processor, and forward theprocessing demand and parameters to the latter step first processor, andtransfer to the processing queue collectively at the final step.
 7. Thecommunication protocol processing unit by a multiprocessor according toclaim 5, wherein each of the plurality of first processors generates theprocessing demand to the second processor, and further transfers thecommunication data or parameters to the processing queueunconditionally, and thereafter the queue can judge independentlyvalidity/invalidity of the data transferred to the processing queueaccording to presence or absence of the processing demands.
 8. Thecommunication protocol processing unit by a multiprocessor according toclaim 6, wherein the processing demands and parameters are structured soas to be laminated in each of the plurality of first processors.
 9. Thecommunication protocol processing unit by a multiprocessor according toclaim 7, wherein the processing demands and parameters are structured soas to be laminated in each of the plurality of first processors.
 10. Thecommunication protocol processing unit by a multiprocessor according toany one of claim 2, wherein the communication data are directlytransferred to the processing queue not via the first processor withreception of the communication data as an event.
 11. A communicationprotocol processing unit by a multiprocessor according to any one ofclaim 1, further comprising: a queue for storing the processing resultsof the second processor in between the first and second processors; anda selection circuit as means for overwriting the communication data on astream to the processing results of the second processor, whereby thefirst processor accesses to read the queue, and switches a selectionroute of the selection circuit to a side of the queue if the data areaccumulated in the queue.
 12. The communication protocol processing unitby a multiprocessor according to claim 11, further comprising: aregister indicating whether or not data are accumulated in the queue forstoring the processing results of the second processor; and a readoutcontrol circuit for reading out the data accumulated in the queue,wherein the first processor does not access the queue, and reads out aset status of the register, thereby recognizing a data accumulation ofthe queue, and wherein the readout control circuit is accumulated whenthe data are accumulated, and reads out the data of the queue not viathe first processor.
 13. The communication protocol processing unit by amultiprocessor according to any one of claim 6, wherein a timing forforwarding the processing demands and parameters is taken with nextreception of the communication data as the event.